Multiprocessor system-on-chip (SOC) platforms are emerging as an important trend for SOC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip, namely, those that incorporate modularity and explicit parallelism. Interconnect fabrics, such as networks-on-chip (NoC), may be used to interconnect the multiple processors and other devices included within the SOC. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements.
Examples of interconnect fabrics that may be used within an SOC include: ARM Inc's AMBA (Advanced Microcontroller Bus Architecture) that defines a multilevel busing system including an AHB (advanced host bus) system bus and an APB (advanced peripheral bus) lower-level peripheral bus; Sonics Inc's proprietary OCP bus, IBM's CoreConnect, Silicore's Wishbone, and Texas Instruments' Common Bus Architecture (CBA).
Most standard bus interfaces claim to support ‘precise’ bursts, meaning that the length of a transaction can be encoded in the interface signaling at the beginning of a transaction. For standard buses which allow master inserted wait states, a bridge simply implements store and forward or passes the wait states on to the destination side of the bridge.